If one considers the signal path that determines the transfer time of data from the instant the external command is generated to the valid transition on the output pad(s) of the data in a generic integrated circuit, as schematically depicted in FIG. 1, it is evident that the electrical characteristics of the signal path in the integrated circuit of certain externally applied commands influences the time taken to complete the operation (cycle). For example, the command may be an external clock signal (CLK) applied on a dedicated input pad of the integrated circuit.
In the sample diagram of FIG. 1, focusing attention on the production of data on an external data bus, it is evident that the output buffer enabling signal OEN and the timing signal CLK are sequential to the response time of the output buffer (Tkqv=time between CLK and DQ_value Valid). External signals AVD and CEN are sequential to enabling timing of the address buffers. Therefore, any propagation delay for all these external signals or commands contributes to determination of the random access time of the integrated device.
Typically, for a memory device, the access time can be divided in three parts: INPUT time (delay between the instant at which a control/address pad assumes a valid value and the instant at which the corresponding internally propagated signal assumes a valid value on the relative internal circuit node), MAIN READ time (time taken to read the data from the array cells), and OUTPUT time (the time taken to transfer the read data to an external BUS).
FIGS. 2A and 2B illustrate certain features of typical internal propagation paths, and FIGS. 3A and 3B illustrate how the two parts, namely the OUTPUT time (or Tkqv) and the INPUT time of the access time are, in turn, sums of distinct delay contributions caused by internal circuit characteristics.
The following main contributions are graphically illustrated in the two FIGS. 3A and 3B:
T1=delay introduced by an input buffer;
T2=delay introduced by the connecting line; and
T3=delay introduced by an output buffer.
Analyzing the time Tkqv, the user generates a leading edge or front edge on the CLK_PAD when ready to accept new data from the device core that, by way of example, may be a nonvolatile flash memory.
Referring to the circuit diagram of FIG. 2B, the CLK signal needs to propagate through an input buffer. The properly dimensioned input buffer drives a metal line that distributes the buffered CLK signal to the flip-flops of all the output buffers. Finally, the data signals pass through the output buffers in order to be made available on the DQ_PADs.
In commercially available flash memory devices, the above-noted delay times are on the order of:
T1˜1.5 ns;
T2˜0.5 ns; and
T3˜5.0 ns.
Similar considerations may be made also for the internal propagation delays of external control signals CEN and AVD of the address data input buffers. Considering the circuitry to which the delay time T1 is attributed, even the minimal circuitry needed to implement an input buffer for a control signal issued by an external user device should at least include two cascaded inverters, one of which is either a NOR gate or a three-state inverter.
FIG. 4 respectively depicts a functional circuit diagram, a detailed electrical circuit diagram and the waveforms on the pad (A) on the intermediate node (B) between the two cascaded inverters and on the driven metal line (C).
The load driven by an input buffer is represented by the metal line that distributes the external control signal to a plurality of output data buffers or to a plurality of input address data buffers, and which has a non-negligible capacitance. This is because the cumulative gate load is driven as well as because the metal line is to be sufficiently large in order not to introduce an intolerable intrinsic delay (excessively resistive) in the propagation of the CLK signal.
Therefore, as a consequence, the two cascaded inverters that constitute an input buffer cannot be of minimal size but at least the second inverter needs to be dimensioned to be able to satisfactorily drive the relatively large load as noted above. However, increasing the size of the inverters could slow down the propagation of the signal onto the capacitive metal line (heavy load). This determines a waveform as indicated by the curve C at the bottom of FIG. 4.
It is evident that there is an opportunity of minimizing or reducing the above-noted delay contributions by achieving faster input buffering.